stage3_ia32_pc.asm

The stage 3 / main kernel for My Operating System (MOS)

This module is responsible for managing and enabling the running of user applications

For software programming, check the System calls section

Author

Marcel Sondaar

License

Educational purposes

Summary

stage3_ia32_pc.asm	The stage 3 / main kernel for My Operating System (MOS)
AP detection and bootstrap	CALL InitializeAPIC ; todo CALL Multiprocessor ; needs fixing
Parse memtable
fix debug stub
Kernel subfunctions
AddGate	allocates a gate and assigns a handler to it
AddThread	adds a new thread to the scheduler’s list
AddBlockedThread	adds a new thread to the blocked list
Starvation in Route functions	add cli/sti blocks to prevent this
AddRoute	adds a name to port lookup to the table
AllocateInterrupt	attempts to allocate an IDT entry of choice
AllocateGDTEntry	Allocates a free slot in the global descriptor table and loads it with the given parameters
AllocateGDTEntry	Allocates and writes a TSS entry in the GDT
AllocateMemoryLo	allocates memory from the table, preferrably from the beginning
AllocateMemoryHi	allocates memory from the table, preferrably from the end
AllocateMemoryUnit	Allocate one unit of free memory from a given table
AllocatePortLo	Attempts to allocate a port in the lower 2k area
AllocatePortHi	Attempts to allocate a port (4) in the higher area
AllocateTaskset	allocates a task set (descriptor + kernel stack page)
AllocateV8086Taskset	allocates a task set (descriptor + kernel stack page)
BootstrapUserspace	load first userspace module and schedule it for execution
subroutine for this
GetGateAddress	Looks up a gate’s values
GetPageEntry	Loads a page table with a given entry
GetPageEntry race condition	mutex on resolver use
GetFPUInfo	Get FPU prescence, detect its type then configure the kernel accordingly
GetProcessorInfo	Gets processor info and configures it accordingly
expand detection for sse3, 3dnow, syscall
AC capability detection
Cyrix detection
GetRoute	Looks up a route in the route table and returns
HardwareDelay	Delays for a short period of time.
InitializeIDT	Sets up the IDT and loads it
InitializeIO	Allocates and fills an IO handout table
InitializeGDT	Sets up the GDT and loads it
InitializeIPC	prepares the data structures needed for inter-process communication
InitializePaging	constructs the page and allocation tables needed for a paged system
InitializePIC	Brings the PIC into a known state
InitializePIT	Brings the PIT into a known state
needs the exact needed frequency calculated	none
InitializeScheduler	prepares and starts the scheduler
InitializeTSS	build the kernel tss from scratch
InitializeTDT	Builds a Task Description Table for the kernel
InsertPage	Loads a page table with a given entry
InsertPageGlobal	loads a page table with a given entry, marking it global
InsertPageUser	loads a page table with a given entry, marking it for userspace
InsertPageDriver	loads a page table with a given entry, marking it both uncacheable and for userspace
InvalidatePage	flushes a page from the TLB.
InstallPatches	checks and runs the patches
ProcessorCOMApatch	for fixing the cyrix 6x86 coma bug
ProcessorF00Fpatch	for installing the workaround for the intel LOCK CMPXCHG8B bug
ProcessorNoFPpatch	changes the #NM interrupt handler to fault (using self-modifying code) instead of switching fpu contexts
write SIMD exception handler
ProcessorSYSEpatch	enables the use of SYSENTER/SYSEXIT instructions
Test SYSENTER/ SYSEXIT - bochs has no clue
ProcessorSYSCpatch	for allowing SYSCALL/SYSRET
ProcessorTLBpatch	replaces InvalidatePage with a more efficient version
SetInterruptEntry	sets and IDT entry
SetInterruptVector	sets the vector for interrupt handling
SetPageEntry	Loads a page table with a given entry
SetTaskRegisters	set GPRs for a given task
Interrupt Handlers
write proper abort handlers
int_nm	handles #NM and switches context for FPU state
fninit bug in 486 and Pentium I series	no-wait instructions can cause an exception in compatibility mode (NE=0) not sure wether we need this as native exceptions seem to be supported in 386+ (it requires mobo circuitry though, might need testing)
thread status checking
Scheduler
scheduler_table	points to the schedule tables for each processor
scheduler_offset	current offsets into the task table
scheduler_curtask	contains the current threads for each processor in TDT/CR3
scheduler_curfpu	Contains the physical address for the TDT currently using the FPU state
scheduler_fpusolv	contains the address of a page that is to contain the TDT when mapped into memory
scheduler_sleeptask	Points to a page containing not-scheduled (blocked) tasks
scheduler_ticks	contains the amount of ticks generated since system startup
scheduler_cr0_ts	local copy of CR0 with TS set
System calls
KernelVersion	Returns the kernel version
MemMap	Maps a certain region in physical space to a region in kernel space
BlockAlloc	Allocates memory and maps it to userspace
race condition on address space allocation	pagetable r/w should be altered so that we can allocate pages for use.
GetTimerTicks	Returns the amount of interrupts the kernel timer has generated
PortAlloc	Requests access to a range of ports
GetCpuInfo	Returns processor name, version and capabilities, independent of CPUID and known cpu bugs.
CreateThread	Creates, Allocates and starts a new thread
RouteAlloc	Requests a name to be bound to a port
RouteFind	Requests to find a gate
GateAlloc	Requests a new gate to be given
GateLookup	Looks up the information of the handler behind a gate
CreateV8086Thread	Creates, Allocates and starts a new thread
sys_kernelswitch	Jump table for the kernel functions
sys_checkprivileges	lookup table for required privileges
sys_privilegeswitch	jump table for kernel calls
Locks
semPageTable	Taken for write lock on page tables
semPortLo	Taken for write lock on lower range port table
semPortHi	Taken for write lock on upper range port table
semBlockedTask	Taken for write access on the blocked task list
semScheduler	Taken for write access to a scheduler’s list
semTaskRoutes	taken for read or write access to the task route map
ticTaskRoutes	ticket counter for the task route map
trnTaskRoutes	turn counter for the task route map
Globals
lpgRamdisk	Ramdisk address
lpgTextPtr	Text video memory address
lpgKernelEndPage	First page after the kernel section
lpgMemtable	Location of memory allocation table in memory
lpgLocalPagedir	Page Directory Mirror address
lpgLocalPagemap	Physical to linear map of the page directory
lpgPageResolver	Temporary location for unpositioned page directories
lpgKernelpager	Location of kernel page table
lpgKernelHole	location of free paging space after kernel stuff
lpgKernelTDT	location of kernel TDT
lpgTaskState	TSS Address
lpgGdtLimit	Global Descriptor Table limit
lpgGdtOffset	Global Descriptor Table offset
lpgIdtLimit	Interrupt Descriptor Table limit
lpgIdtOffset	Interrupt Descriptor Table offset
lpgIdtAllocators	Location of interrupt owners
lpgIOMapOffset	Location of port allocation tables
lpgTSSDescriptor	Kernel thread TSS descriptor
lpgTSSaddress	Kernel thread TSS address
lpgSchedulerIndex	Scheduler index page
lpgTickCount	Amount of milliseconds since kernel initialisation
lpgLAPICBase	Base address for the onboard local APIC
lpgProcessorcount	amount of Processors in the system
lpgBootstrapApic	the APIC ID of the bootstrap processor
lpgProcessorType	the installed processor type
lpgProcessorVersion	the packed version word, 4 bits a number (x.x.x.x)
lpgProcessorName	processor type
lpgProcessorCaps	the installed processor’s capabilities
lpgTaskRoutes	pointer to an name-to-port table
lpgTaskHandlers	pointer to a task-lookup table

AP detection and bootstrap

CALL InitializeAPIC ; todo CALL Multiprocessor ; needs fixing

Parse memtable

fix debug stub

Kernel subfunctions

AddGate

allocates a gate and assigns a handler to it

in

EBX	CR3 of the gate’s handler
EDI	the handler’s function

out

EDX	Gate number allocated

destroyed

ECX

AddThread

adds a new thread to the scheduler’s list

in

ESI	CR3 of the thread to be added
EDI	TDT location
EAX	processor to schedule to

out

CF	clear on success, set on failure

destroyed

ECX

AddBlockedThread

adds a new thread to the blocked list

in

ESI	CR3 of the thread to be added
EDI	TDT location

out

CF	clear on success, set on failure

destroyed

EAX ECX

Starvation in Route functions

add cli/sti blocks to prevent this

AddRoute

adds a name to port lookup to the table

in

EAX	port number
EDX	route name

out

CF	clear on success, set on failure

destroyed

none

AllocateInterrupt

attempts to allocate an IDT entry of choice

in

AL = interrupt number

out

CF = clear on success

destroyed

EBX EDX

AllocateGDTEntry

Allocates a free slot in the global descriptor table and loads it with the given parameters

in

EBX = lo dword
EDX = hi dword

out

EAX = descriptor
EDX = linear offset of the current descriptor

destroyed

EAX EBX ECX EDX

AllocateGDTEntry

Allocates and writes a TSS entry in the GDT

in

EDI = address of free memory

out

EAX = descriptor

destroyed

EAX EBX ECX EDX

AllocateMemoryLo

allocates memory from the table, preferrably from the beginning

in

none

out

EAX = physical address
CF = clear on success

destroyed

none

AllocateMemoryHi

allocates memory from the table, preferrably from the end

in

none

out

EAX = physical address
CF = clear on success

destroyed

none

AllocateMemoryUnit

Allocate one unit of free memory from a given table

in

EAX = Subtable Address

out

EAX = page relative to this table
CF = set on failure

destroyed

none

AllocatePortLo

Attempts to allocate a port in the lower 2k area

in

EDX = requested port

out

CF = clear on success

destroyed

none

AllocatePortHi

Attempts to allocate a port (4) in the higher area

in

EDX = requested port

out

CF = clear on success

destroyed

none

AllocateTaskset

allocates a task set (descriptor + kernel stack page)

in

EDI = virtual address to allocate at
EBX = virtual address to start execution

out

CF = clear on success
EAX = thread handle
EDI = virual address of task descriptor

destroyed

ECX, ESI

AllocateV8086Taskset

allocates a task set (descriptor + kernel stack page)

in

EDI = virtual address to allocate at
EBX = packed cs:ip to start execution at

out

CF = clear on success
EAX = thread handle
EDI = virual address of task descriptor

destroyed

ECX, ESI

BootstrapUserspace

load first userspace module and schedule it for execution

the file is named ‘STAGE4’ and is considered a flat binary and is loaded and executed at the 4mb mark

in

none

out

none

destroyed

all non-stack registers

subroutine for this

GetGateAddress

Looks up a gate’s values

in

EAX	gate number

out

EDX	CR3
EBX	Address

destroyed

none

GetPageEntry

Loads a page table with a given entry

in

EDI = location to check

out

ESI = page table entry

destroyed

EAX EBX EDX

GetPageEntry race condition

mutex on resolver use

GetFPUInfo

Get FPU prescence, detect its type then configure the kernel accordingly

in

none

out

none

destroyed

EAX

GetProcessorInfo

Gets processor info and configures it accordingly

in

none

out

none

destroyed

all non-stack registers

expand detection for sse3, 3dnow, syscall

AC capability detection

Cyrix detection

GetRoute

Looks up a route in the route table and returns

in

EDX	route name

out

EAX	route port, or 0 on failure

destroyed

none

HardwareDelay

Delays for a short period of time.

in

none

out

none

destroyed

none

InitializeIDT

Sets up the IDT and loads it

in

none

out

none

destroyed

all non-stack registers

InitializeIO

Allocates and fills an IO handout table

Only 16k ports can be accessed. (Some ISA cards dont decode the top bits anyway)

The first 2k ports are fine grained to one address (0x0000-0x0800). The remaining 14k ports are handed out in doubleword accesses (4 consecutive addresses). A short integer is used to count the amount of allocations for the given port. This requires 1x 4k page for the low addresses and 2x 4k pages for the high addresses, adding to 12k of memory (with some redundancy)

PIT, PIC1 and PIC2 are claimed by default

in

none

out

none

destroyed

all non-stack registers

InitializeGDT

Sets up the GDT and loads it

in

none

out

none

destroyed

all non-stack registers

InitializeIPC

prepares the data structures needed for inter-process communication

right now that only involves allocating two pages and zeroing them

in

none

out

none

destroyed

all non-task registers

InitializePaging

constructs the page and allocation tables needed for a paged system

fixed pages after the kernel

memory

(+0) Memory Allocation Directory
(+1) Memory Allocation Page (for the first 4mb)
(+2) Kernel Page Directory
(+3) Kernel Linear-to-physical map
(+4) Kernel Page Table (first 4mb)
(+5) Stack address space
(+0) Memory Allocation Directory
(+1) Memory Allocation Page (for the first 4mb)
(+2) Kernel Page Directory
(+3) Physical-linear mapping of entries
(+4) Kernel Page Table (first 4mb)
(+5) Stack
(+6) Page directory resolve area

in

none

out

none

destroyed

all non-stack registers

InitializePIC

Brings the PIC into a known state

maps the irq’s 0-15 to the non-intel area

in

none

out

none

destroys

EAX, EBX

InitializePIT

Brings the PIT into a known state

programs channel 0 to a ~100hz rate generator some bioses do not pre-load the pit to 18hz rate making this step necessary to get a regular interrupt issued on those systems

needs the exact needed frequency calculated

in

none

out

none

destroys

EAX, EBX

InitializeScheduler

prepares and starts the scheduler

in

none

out

none

destroyed

all non-task registers

InitializeTSS

build the kernel tss from scratch

in

none

out

none

destroyed

all non-task registers

InitializeTDT

Builds a Task Description Table for the kernel

in

none

out

none

destroyed

all non-task registers

InsertPage

Loads a page table with a given entry

in

ESI = page to address
EDI = location to insert to

out

none

destroyed

EAX EBX EDX

InsertPageGlobal

loads a page table with a given entry, marking it global

in

ESI = page to address
EDI = location to insert to

out

none

destroyed

EAX EBX EDX

InsertPageUser

loads a page table with a given entry, marking it for userspace

in

ESI = page to address
EDI = location to insert to

out

none

destroyed

EAX EBX EDX

InsertPageDriver

loads a page table with a given entry, marking it both uncacheable and for userspace

in

ESI = page to address
EDI = location to insert to

out

none

destroyed

EAX EBX EDX

InvalidatePage

flushes a page from the TLB. On 386’s it has to flush the entire TLB

patched by <ProcessorTLBPatch>

in

EDI = address to be invalidated

out

none

destroyed

none

InstallPatches

checks and runs the patches

ProcessorCOMApatch

for fixing the cyrix 6x86 coma bug

ProcessorF00Fpatch

for installing the workaround for the intel LOCK CMPXCHG8B bug

in

none

out

none

destroyed

none

ProcessorNoFPpatch

changes the #NM interrupt handler to fault (using self-modifying code) instead of switching fpu contexts

in

none

out

none

destroyed

none

write SIMD exception handler

ProcessorSYSEpatch

enables the use of SYSENTER/SYSEXIT instructions

in

none

out

none

destroyed

none

Test SYSENTER/ SYSEXIT - bochs has no clue

ProcessorSYSCpatch

for allowing SYSCALL/SYSRET

ProcessorTLBpatch

replaces InvalidatePage with a more efficient version

patch highly recommended on 486 or better patch breaks 386s

in

none

out

none

destroyed

none

SetInterruptEntry

sets and IDT entry

in

AL = interrupt number
EBX = hi dword
EDX = lo dword

out

none

destroyed

none

SetInterruptVector

sets the vector for interrupt handling

in

AL = interrupt number
EDI = location of interrupt handler

out

none

destroyed

unknown

SetPageEntry

Loads a page table with a given entry

in

ESI = page table entry
EDI = location to insert to

out

none

destroyed

EAX EBX EDX

SetTaskRegisters

set GPRs for a given task

in

EDI = TDT to modify, must not be scheduled
EAX = task’s new EAX
EBX = task’s new EBX
ECX = task’s new ECX
EDX = task’s new EDX
ESI = task’s new EBP

out

none

destroyed

none

Interrupt Handlers

write proper abort handlers

int_nm

handles #NM and switches context for FPU state

Patched by <processorNoFPpatch>

interrupt handler

fninit bug in 486 and Pentium I series

no-wait instructions can cause an exception in compatibility mode (NE=0) not sure wether we need this as native exceptions seem to be supported in 386+ (it requires mobo circuitry though, might need testing)

thread status checking

Scheduler

scheduler_table

scheduler_table: TIMES 8 DD 0

points to the schedule tables for each processor

scheduler_offset

scheduler_offset: TIMES 8 DD 0

current offsets into the task table

scheduler_curtask

scheduler_curtask: TIMES 8 * 2 DD 0

contains the current threads for each processor in TDT/CR3

scheduler_curfpu

scheduler_curfpu: TIMES 8 DD 0

Contains the physical address for the TDT currently using the FPU state

scheduler_fpusolv

scheduler_fpusolv: TIMES 8 DD 0

contains the address of a page that is to contain the TDT when mapped into memory

scheduler_sleeptask

scheduler_sleeptask:DD 0

Points to a page containing not-scheduled (blocked) tasks

scheduler_ticks

scheduler_ticks: DD 0

contains the amount of ticks generated since system startup

scheduler_cr0_ts

scheduler_cr0_ts: DD 0

local copy of CR0 with TS set

System calls

KernelVersion

Returns the kernel version

Privilege level

Informational

in

EAX = 0x00000000

out

EAX = version: bits 0-15 = revision, 16-23 = minor, 24-31 = major

destroyed

none

MemMap

Maps a certain region in physical space to a region in kernel space

Use with caution as this function does not perform any sanity checks

Privilege level

Kernel

in

EAX = 0x00010000
EBX = amount of pages to map
ESI = starting page in physical memory
EDI = starting page in current address space

out

EBX = 0

destroyed

EAX EDX

BlockAlloc

Allocates memory and maps it to userspace

Returns the amount of memory actually mapped

Privilege level

User

in

EAX = 0x00020000
EBX = amount of memory to map (bytes)
EDI = starting page in current address space

out

EBX = amount of memory actually mapped

destroyed

EAX EDX

race condition on address space allocation

pagetable r/w should be altered so that we can allocate pages for use. Right now its either checked inconsistently or blindly written

GetTimerTicks

Returns the amount of interrupts the kernel timer has generated

Privilege leel

User

in

EAX = 0x00030000

out

EAX = number of ticks occurred

destroyed

none

PortAlloc

Requests access to a range of ports

Privilege Level

Driver

in

EAX	0x00040000
EDI	First port to be opened
EBX	Amount of ports to be opened

out

EAX	Amount of ports allocated. Success if EAX >= EBX

destroyed

unknown

GetCpuInfo

Returns processor name, version and capabilities, independent of CPUID and known cpu bugs.

Data is generated by GetProcessorInfo

Privilege Level

Informational

in

EAX	0x00050000
EBX	CPU number (zero based)

out

EBX	name 0-3
EDX	name 4-7
ECX	name 8-11
EAX	first set of capabilities
ESI	second set of capabilities
EDI	packed processor version 24-31: model shortcut 15-12: type 11-08: family 07-04: model 03-00: revision
CF	clear if present, set if not present if set, the rest of the output is not changed

destroyed

none

CreateThread

Creates, Allocates and starts a new thread

Privilege Level

User level

in

EAX	0x000
EBX	Address of the thread to be started
EDI	Linear Address where the information is to be stored60000

out

EAX	amount of bytes allocated
CF	clear on success, set on failure

destroyed

ECX ESI

RouteAlloc

Requests a name to be bound to a port

Privilege Level

Driver

in

EAX	0x00070000
EBX	Route to be allocated
EDI	Port to point at

out

CF	clear on success, set on failure

destroyed

EAX EDX

RouteFind

Requests to find a gate

Privilege Level

User

in

EAX	0x00080000
EBX	Name to check

out

EAX	gate associated with the requested name, or 0 if it wasnt found

destroyed

EDX

GateAlloc

Requests a new gate to be given

Privilege Level

User

in

EAX	0x00090000
EDI	Pointer to the handler function

out

EAX	number of the acquired gate

destroyed

ECX EDX

GateLookup

Looks up the information of the handler behind a gate

Privilege Level

User

in

EAX	0x000A0000
EBX	gate number

out

EAX	Address Space Handle of the handler
EBX	Pointer of the handler function

destroyed

EDX

CreateV8086Thread

Creates, Allocates and starts a new thread

Privilege Level

User level

in

EAX	0x000B0000
EBX	CS:IP value to start execution
EDI	Linear Address where the information is to be stored

out

EAX	amount of bytes allocated
CF	clear on success, set on failure

destroyed

ECX ESI

sys_kernelswitch

Jump table for the kernel functions

sys_checkprivileges

lookup table for required privileges

sys_privilegeswitch

jump table for kernel calls

Locks

semPageTable

semPageTable: DB 1

Taken for write lock on page tables

semPortLo

semPortLo: DB 1

Taken for write lock on lower range port table

semPortHi

semPortHi: DB 1

Taken for write lock on upper range port table

semBlockedTask

semBlockedTask: DB 1

Taken for write access on the blocked task list

semScheduler

semScheduler: DB 0xff

Taken for write access to a scheduler’s list

semTaskRoutes

semTaskRoutes: DB 1

taken for read or write access to the task route map

ticTaskRoutes

ticTaskRoutes: DW 0

ticket counter for the task route map

trnTaskRoutes

trnTaskRoutes: DW 0

turn counter for the task route map

Globals

lpgRamdisk

lpgRamdisk: DD 0

Ramdisk address

lpgTextPtr

lpgTextPtr: DD 0

Text video memory address

lpgKernelEndPage

lpgKernelEndPage: DD 0

First page after the kernel section

lpgMemtable

Location of memory allocation table in memory

lpgLocalPagedir

Page Directory Mirror address

lpgLocalPagemap

Physical to linear map of the page directory

lpgPageResolver

lpgPageResolver: DD 0

Temporary location for unpositioned page directories

lpgKernelpager

Location of kernel page table

lpgKernelHole

lpgKernelHole: DD 0

location of free paging space after kernel stuff

lpgKernelTDT

lpgKernelTDT: DD 0

location of kernel TDT

lpgTaskState

lpgTaskState: DD 0

TSS Address

lpgGdtLimit

lpgGdtLimit: DW 0xffff

Global Descriptor Table limit

lpgGdtOffset

lpgGdtOffset: DD 0

Global Descriptor Table offset

lpgIdtLimit

lpgIdtLimit: DW 0x7ff

Interrupt Descriptor Table limit

lpgIdtOffset

lpgIdtOffset: DD 0

Interrupt Descriptor Table offset

lpgIdtAllocators

lpgIdtAllocators: DD 0

Location of interrupt owners

lpgIOMapOffset

lpgIOMapOffset: DD 0

Location of port allocation tables

lpgTSSDescriptor

lpgTSSDescriptor: DW 0

Kernel thread TSS descriptor

lpgTSSaddress

lpgTSSaddress: DD 0

Kernel thread TSS address

lpgSchedulerIndex

lpgSchedulerIndex: DD 0

Scheduler index page

lpgTickCount

lpgTickCount: DD 0, 0

Amount of milliseconds since kernel initialisation

lpgLAPICBase

lpgLAPICBase: DD 0

Base address for the onboard local APIC

lpgProcessorcount

lpgProcessorcount: DB 1

amount of Processors in the system

lpgBootstrapApic

lpgBootstrapApic: DB 0

the APIC ID of the bootstrap processor

lpgProcessorType

lpgProcessorType: DB 0

the installed processor type

lpgProcessorVersion

lpgProcessorVersion:DW 0

the packed version word, 4 bits a number (x.x.x.x)

lpgProcessorName

lpgProcessorName: DB "UndefinedCPU"

processor type

lpgProcessorCaps

lpgProcessorCaps: DD 0

the installed processor’s capabilities

lpgTaskRoutes

lpgTaskRoutes: DD 0

pointer to an name-to-port table

lpgTaskHandlers

lpgTaskHandlers: DD 0

pointer to a task-lookup table