verite.bi

Contains the register definitions for the Rendition Verite video cards (V1000 and V2x00)

Author

Marcel Sondaar

Summary

verite.bi	Contains the register definitions for the Rendition Verite video cards (V1000 and V2x00)
VREGS	Registers common to all Verite-based boards
Constants
VERITE_MEMENDIAN	This register controls the byteswapping performed when writing to the linear framebuffer.
VERITE_GPUCTL	This register controls the state of the RISC processor It holds several bitflags:
VERITE_GPUSTAT	This register contains the current status of the device Only present on V2x00
VERITE_GPUINDEX	index register to the GPU external registers
VERITE_GPUDATA	This register contains the value of the GPU register selected by VERITE_GPUINDEX.
VERITE_MODE	This register allows one to select between CRTC modes.
VERITE_CRTCCTL	CRTC Control register.
VERITE_CRTCH	Horizontal timing register
VERITE_CRTCV	Vertical timing register
VERITE_FRAMESTART	Frame offset
VERITE_WIDTH	Virtual width?
VERITE_DAC_PIXELMASK	RAMDAC configuration
VERITE_DAC_CR0	RAMDAC configuration
VERITE_DAC_CR1	RAMDAC configuration
VERITE_DAC_CR2	RAMDAC configuration
VERITE_DOTCLOCK	Access to the V2x00 dot clock PLL
VINSNS	List of verite GPU opcodes Each instruction is exactly 32-bits, of the form ooxxxxxx, where oo is the opcode and xx are the arguments Most opcodes follow a triadic instruction: ooddxxyy, where dd is destination register, xx and yy are source registers Jumps are pipelined and therefore have a delay of a cycle.
Constants
VINSN_ADDI	Add a register and a byte immediate
VINSN_SUBI	Subtract a byte immediate from a register
VINSN_ANDNI	Computes the binary and-not of a register and a byte immediate
VINSN_RSUBI	Subtract a register from a byte immediate
VINSN_ANDI	Computes the inclusive or of a register and a byte immediate
VINSN_ORI	Computes the inclusive or of a register and a byte immediate
VINSN_NORI	Computes the binary nor of a register and a byte immediate
VINSN_XORI	Computes the exclusive or of a register and a byte immediate
VINSN_ADD	add two registers and put the result in the target register
VINSN_SUB	subtract the second source from the first source register and put the result in the target register
VINSN_ANDN	compute the and-not of two registers and put the result in the target register
VINSN_RSUB	subtract the first source register from the second source register and put the result in the target register
VINSN_AND	compute the binary and of two registers and put the result in the target register
VINSN_OR	compute the binary inclusive or of two registers and put the result in the target register
VINSN_NOR	compute the binary nor two registers and put the result in the target register
VINSN_XOR	compute the binary exclusive or of two registers and put the result in the target register
VINSN_RFIFO	Pops a slot from the FIFO, stall if the fifo is empty.
fixme-VINSN_PLD16I	load the high 16 bits of a register with an immediate value
VINSN_RORI	rotate register right by a constant number of positions.
VINSN_SHLI	shift register right by a constant number of positions, sign extending in the process.
VINSN_SARI	shift register right by a constant number of positions, sign extending in the process.
VINSN_SHRI	shift register right by a constant number of positions, adding zeros on the far end
fixme-VINSN_PLD8I	load the high 24 bits of a register with an immediate value
VINSN_JZ	Jump conditional if register is zero
VINSN_JNZ	Jump conditional if register is non-zero
VINSN_JS	Jump conditional if register is negative
VINSN_JNS	Jump conditional if register is not negative
VINSN_JA	Jump conditional if register is above zero
VINSN_JNA	Jump conditional if register is not above zero
VINSN_JMP	Jump to an absolute address
VINSN_JMPR	Jump to address specified in register
VINSN_LDB. The result is not available until after the next cycle.	Load a byte from RAM
VINSN_LDH	Load a 16-bit halfword from RAM.
VINSN_LDW	Load a 32-bit word from RAM.
VINSN_LDI	Load an 16-bit immediate into the selected register
VINSN_LDHI	Load a shifted 16-bit immediate into the selected register.

VREGS

Registers common to all Verite-based boards

Summary

Constants
VERITE_MEMENDIAN	This register controls the byteswapping performed when writing to the linear framebuffer.
VERITE_GPUCTL	This register controls the state of the RISC processor It holds several bitflags:
VERITE_GPUSTAT	This register contains the current status of the device Only present on V2x00
VERITE_GPUINDEX	index register to the GPU external registers
VERITE_GPUDATA	This register contains the value of the GPU register selected by VERITE_GPUINDEX.
VERITE_MODE	This register allows one to select between CRTC modes.
VERITE_CRTCCTL	CRTC Control register.
VERITE_CRTCH	Horizontal timing register
VERITE_CRTCV	Vertical timing register
VERITE_FRAMESTART	Frame offset
VERITE_WIDTH	Virtual width?
VERITE_DAC_PIXELMASK	RAMDAC configuration
VERITE_DAC_CR0	RAMDAC configuration
VERITE_DAC_CR1	RAMDAC configuration
VERITE_DAC_CR2	RAMDAC configuration
VERITE_DOTCLOCK	Access to the V2x00 dot clock PLL

Constants

VERITE_MEMENDIAN

This register controls the byteswapping performed when writing to the linear framebuffer.

Size

8 bits

valid register values

0	no byteswapping
1	32-bit byteswapping
2	16-bit byteswapping
3	swap halfwords

VERITE_GPUCTL

This register controls the state of the RISC processor It holds several bitflags:

Size

unknown

Bitflags

01h	reset chip
02h	hold risc. Setting this bit will stop the main GPU from executing more instructions
04h	single step. Setting this bit will cause a single step in the pipeline to be executed. The bit will be cleared by the GPU when the instruction is executed.
08h	divide by 2 disable
10h	VGA reset
20h	assert XReset output to ext devices

VERITE_GPUSTAT

This register contains the current status of the device Only present on V2x00

Size

unknown

02h

risc held

VERITE_GPUINDEX

index register to the GPU external registers

Size

unknown

Values

80	Intruction Register
82	Status Register 1

VERITE_GPUDATA

This register contains the value of the GPU register selected by VERITE_GPUINDEX. A write will load the corresponding GPU register

VERITE_MODE

This register allows one to select between CRTC modes. One can choose between VGA, VESA and Native mode by encoding the proper bits

Size

8 bits

Bitflags

01h	Decode 0xA0000.
02h	Operate in VGA Mode. This will enable A0000-BFFFF indepent of bit 1
04h	32-bit VGA

VERITE_CRTCCTL

CRTC Control register. 32-bits in size, contains several flags and pixel formats

Size

32 bits

Bitflags

0000000F	color format
00000010	CRTCCTL_VIDEOFIFOSIZE128
00000020	CRTCCTL_ENABLEDDC
00000040	CRTCCTL_DDCOUTPUT
00000080	CRTCCTL_DDCDATA
00000100	CRTCCTL_VSYNCHI
00000200	CRTCCTL_HSYNCHI
00000400	CRTCCTL_VSYNCENABLE
00000800	CRTCCTL_HSYNCENABLE
00001000	CRTCCTL_VIDEOENABLE
00002000	CRTCCTL_STEREOSCOPIC
00004000	CRTCCTL_FRAMEDISPLAYED
00008000	CRTCCTL_FRAMEBUFFERBGR
00010000	CRTCCTL_EVENFRAME
00020000	CRTCCTL_LINEDOUBLE
00040000	CRTCCTL_FRAMESWITCHED

Color formats

4	16 bpp (R5-G6-B5)
5	16 bpp (R4-G4-B4-X4)
12	32 bpp (R8-G8-B8-X8)

VERITE_CRTCH

Horizontal timing register

Size

32 bits

VERITE_CRTCV

Vertical timing register

Size

32 bits

VERITE_FRAMESTART

Frame offset

Size

unknown

VERITE_WIDTH

Virtual width?

Size

32 bits

VERITE_DAC_PIXELMASK

RAMDAC configuration

Size

8 bits

VERITE_DAC_CR0

RAMDAC configuration

Size

8 bits

VERITE_DAC_CR1

RAMDAC configuration

Size

8 bits

Bitfields

08	Use 565 RGB
10	Bypass color lookup (disable palette)
E0	Bits per pixel 00 = 24 bits 20 = 16 bits 40 = 8 bits 60 = 4 bits

VERITE_DAC_CR2

RAMDAC configuration

Size

8 bits

VERITE_DOTCLOCK

Access to the V2x00 dot clock PLL

Size

unknown

Bitfields

VINSNS

List of verite GPU opcodes Each instruction is exactly 32-bits, of the form ooxxxxxx, where oo is the opcode and xx are the arguments Most opcodes follow a triadic instruction: ooddxxyy, where dd is destination register, xx and yy are source registers Jumps are pipelined and therefore have a delay of a cycle.

Summary

Constants
VINSN_ADDI	Add a register and a byte immediate
VINSN_SUBI	Subtract a byte immediate from a register
VINSN_ANDNI	Computes the binary and-not of a register and a byte immediate
VINSN_RSUBI	Subtract a register from a byte immediate
VINSN_ANDI	Computes the inclusive or of a register and a byte immediate
VINSN_ORI	Computes the inclusive or of a register and a byte immediate
VINSN_NORI	Computes the binary nor of a register and a byte immediate
VINSN_XORI	Computes the exclusive or of a register and a byte immediate
VINSN_ADD	add two registers and put the result in the target register
VINSN_SUB	subtract the second source from the first source register and put the result in the target register
VINSN_ANDN	compute the and-not of two registers and put the result in the target register
VINSN_RSUB	subtract the first source register from the second source register and put the result in the target register
VINSN_AND	compute the binary and of two registers and put the result in the target register
VINSN_OR	compute the binary inclusive or of two registers and put the result in the target register
VINSN_NOR	compute the binary nor two registers and put the result in the target register
VINSN_XOR	compute the binary exclusive or of two registers and put the result in the target register
VINSN_RFIFO	Pops a slot from the FIFO, stall if the fifo is empty.
fixme-VINSN_PLD16I	load the high 16 bits of a register with an immediate value
VINSN_RORI	rotate register right by a constant number of positions.
VINSN_SHLI	shift register right by a constant number of positions, sign extending in the process.
VINSN_SARI	shift register right by a constant number of positions, sign extending in the process.
VINSN_SHRI	shift register right by a constant number of positions, adding zeros on the far end
fixme-VINSN_PLD8I	load the high 24 bits of a register with an immediate value
VINSN_JZ	Jump conditional if register is zero
VINSN_JNZ	Jump conditional if register is non-zero
VINSN_JS	Jump conditional if register is negative
VINSN_JNS	Jump conditional if register is not negative
VINSN_JA	Jump conditional if register is above zero
VINSN_JNA	Jump conditional if register is not above zero
VINSN_JMP	Jump to an absolute address
VINSN_JMPR	Jump to address specified in register
VINSN_LDB. The result is not available until after the next cycle.	Load a byte from RAM
VINSN_LDH	Load a 16-bit halfword from RAM.
VINSN_LDW	Load a 32-bit word from RAM.
VINSN_LDI	Load an 16-bit immediate into the selected register
VINSN_LDHI	Load a shifted 16-bit immediate into the selected register.

Constants

VINSN_ADDI

Add a register and a byte immediate

Format

00 dd ss xx

dd	destination register
ss	source register
xx	byte value

operation

dd = ss + xx

VINSN_SUBI

Subtract a byte immediate from a register

Format

01 dd ss xx

dd	destination register
ss	source register
xx	byte value

operation

dd = ss

VINSN_ANDNI

Computes the binary and-not of a register and a byte immediate

Format

02 dd ss xx

dd	destination register
ss	source register
xx	byte value

operation

dd = ss & ~xx

VINSN_RSUBI

Subtract a register from a byte immediate

Format

03 dd ss xx

dd	destination register
ss	source register
xx	byte value

operation

dd = xx

VINSN_ANDI

Computes the inclusive or of a register and a byte immediate

Format

04 dd ss xx

dd	destination register
ss	source register
xx	byte value

operation

dd = ss & xx

VINSN_ORI

Computes the inclusive or of a register and a byte immediate

Format

05 dd ss xx

dd	destination register
ss	source register
xx	byte value

operation

dd = ss | xx

VINSN_NORI

Computes the binary nor of a register and a byte immediate

Format

06 dd ss xx

dd	destination register
ss	source register
xx	byte value

operation

dd = ~ (ss | xx)

VINSN_XORI

Computes the exclusive or of a register and a byte immediate

Format

07 dd ss xx

dd	destination register
ss	source register
xx	byte value

operation

dd = ss ^ xx

VINSN_ADD

add two registers and put the result in the target register

format

10 dd xx yy

dd	destination register
xx	source register 1
yy	source register

operation

dd = xx + yy

VINSN_SUB

subtract the second source from the first source register and put the result in the target register

format

11 dd xx yy

dd	destination register
xx	source register 1
yy	source register

operation

dd = xx

VINSN_ANDN

compute the and-not of two registers and put the result in the target register

format

12 dd xx yy

dd	destination register
xx	source register 1
yy	source register

operation

dd = xx & ~yy

VINSN_RSUB

subtract the first source register from the second source register and put the result in the target register

format

13 dd xx yy

dd	destination register
xx	source register 1
yy	source register

operation

dd = yy

VINSN_AND

compute the binary and of two registers and put the result in the target register

format

14 dd xx yy

dd	destination register
xx	source register 1
yy	source register

operation

dd = xx & yy

VINSN_OR

compute the binary inclusive or of two registers and put the result in the target register

format

15 dd xx yy

dd	destination register
xx	source register 1
yy	source register

operation

dd = xx | yy

VINSN_NOR

compute the binary nor two registers and put the result in the target register

format

16 dd xx yy

dd	destination register
xx	source register 1
yy	source register

operation

dd = ~(xx | yy)

VINSN_XOR

compute the binary exclusive or of two registers and put the result in the target register

format

17 dd xx yy

dd	destination register
xx	source register 1
yy	source register

operation

dd = xx ^ yy

VINSN_RFIFO

Pops a slot from the FIFO, stall if the fifo is empty.

format

43 dd xx yy

dd	destination register
xx	mask register (between 0 and F)
yy	control byte

operation

dd = fifo.pop() & xx

The mask does not seem to work properly with general purpose registers. The following can be used consistently

08	and the fifo value with 0xffff0000
0D	mask with 0xffffffff (i.e. read all bytes)

The control byte specifies one of the fifo formats

20	read fifo in big-endian format
21	read fifo in little-endian format

fixme-VINSN_PLD16I

load the high 16 bits of a register with an immediate value

format

40 dd ss xx

dd	destination register
ss	source register
xx	byte immediate

operation

dd = (ss & 0xffff) | (xx << 16)

VINSN_RORI

rotate register right by a constant number of positions.

format

44 dd ss xx

dd	destination register
ss	source register
xx	byte immediate

operation

dd = ss ROR xx

VINSN_SHLI

shift register right by a constant number of positions, sign extending in the process.

format

45 dd ss xx

dd	destination register
ss	source register
xx	byte immediate

operation

dd = ss << xx

VINSN_SARI

shift register right by a constant number of positions, sign extending in the process.

format

46 dd ss xx

dd	destination register
ss	source register
xx	byte immediate

operation

dd = ss >>> xx

VINSN_SHRI

shift register right by a constant number of positions, adding zeros on the far end

format

47 dd ss xx

dd	destination register
ss	source register
xx	byte immediate

operation

dd = ss >> xx

fixme-VINSN_PLD8I

load the high 24 bits of a register with an immediate value

format

4b dd ss xx

dd	destination register
ss	source register
xx	byte immediate

operation

dd = (ss & 0xff) | (xx << 8)

VINSN_JZ

Jump conditional if register is zero

format

60 nn nn ss

nnnn	signed 16-bit displacement. Contains the number of instructions to jump if the condition is met. A displacement of -1 would be the jump instruction.
ss	the source register whose contents to check

operation

if (ss = 0) schedule_jump(pc+4

4*nnnn)

VINSN_JNZ

Jump conditional if register is non-zero

format

61 nn nn ss

nnnn	signed 16-bit displacement. Contains the number of instructions to jump if the condition is met. A displacement of -1 would be the jump instruction.
ss	the source register whose contents to check

operation

if (ss != 0) schedule_jump(pc+4

4*nnnn)

VINSN_JS

Jump conditional if register is negative

format

62 nn nn ss

nnnn	signed 16-bit displacement. Contains the number of instructions to jump if the condition is met. A displacement of -1 would be the jump instruction.
ss	the source register whose contents to check

operation

if (ss < 0) schedule_jump(pc+4

4*nnnn)

VINSN_JNS

Jump conditional if register is not negative

format

63 nn nn ss

nnnn	signed 16-bit displacement. Contains the number of instructions to jump if the condition is met. A displacement of -1 would be the jump instruction.
ss	the source register whose contents to check

operation

if (ss >= 0) schedule_jump(pc+4

4*nnnn)

VINSN_JA

Jump conditional if register is above zero

format

64 nn nn ss

nnnn	signed 16-bit displacement. Contains the number of instructions to jump if the condition is met. A displacement of -1 would be the jump instruction.
ss	the source register whose contents to check

operation

if (ss > 0) schedule_jump(pc+4

4*nnnn)

VINSN_JNA

Jump conditional if register is not above zero

format

64 nn nn ss

nnnn	signed 16-bit displacement. Contains the number of instructions to jump if the condition is met. A displacement of -1 would be the jump instruction.
ss	the source register whose contents to check

operation

if (ss > 0) schedule_jump(pc+4

4*nnnn)

VINSN_JMP

Jump to an absolute address

format

6c nn nn nn

nnnnnn

24-bit absolute jump target. This value is shifted left by two to create the actual address (and keep the program counter dword aligned)

VINSN_JMPR

Jump to address specified in register

format

6f xx xx nn

nn	The register that holds the jump target.
xxxx	unused?

VINSN_LDB. The result is not available until after the next cycle.

Load a byte from RAM

format

70 dd xx ss

dd	destination register
xx	unsigned immediate displacement
ss	memory offset register

operation

dd = mem[ss + xx]

VINSN_LDH

Load a 16-bit halfword from RAM. The result is not available until after the next cycle.

format

71 dd xx ss

dd	destination register
xx	unsigned immediate displacement
ss	memory offset register

operation

dd = mem[ss + 2*xx]

VINSN_LDW

Load a 32-bit word from RAM. The result is not available until after the next cycle.

format

72 dd xx ss

dd	destination register
xx	unsigned immediate displacement
ss	memory offset register

operation

dd = mem[ss + 4*xx]

VINSN_LDI

Load an 16-bit immediate into the selected register

format

76 dd nn nn

dd	destination register
nnnn	16 bit constant

operation

dd = nnnn

VINSN_LDHI

Load a shifted 16-bit immediate into the selected register.

format

76 dd nn nn

dd	destination register
nnnn	16 bit constant

operation

dd = nnnn << 16